\section{JEdifBuild Options}
JEdifBuild creates merged netlists in a .jedif file format from
multiple .edf files. By default, JEdifBuild also flattens the design
and optionally performs FMAP removal, RLOC removal, SRL replacement,
and half-latch removal (functions performed by JEdifSterilize in
previous versions of the toolflow). The .jedif file format is an
intermediate file format used by the remainder of the replication
tools.

Although flattening occurs by default, it can be disabled with the
\texttt{--no\_flatten} option. It is also possible to specify that specific
cell types should not be flattened. This can be accomplished by adding a
\texttt{`do\_not\_flatten'} property to the cell in the .edf file as follows:\\
\texttt{(property do\_not\_flatten (boolean (true)))}

If this property is used on a cell that is a black box in the main design file
and is merged in from a separate .edf or .edn file, the property should be
specified in the black box \emph{definition} file, not in the main design .edf
file.

It should be noted that designs that are not flattened will not be replicated
properly. Any unflattened cells will be replicated as an atomic unit,
preventing proper voter insertion. Use the \texttt{`do\_not\_flatten'} property
only when this is the desired behavior.

Cell types that are selected as pre-mitigated cells using \texttt{`port\_group'}
properties (see Section~\ref{sec:pre-mitigation}) are also left unflattened.
Flattening for pre-mitigated cells is not necessary since they will not be replicated.

Options can be specified on the command line or in a configuration file in any 
order. This section describes each of these options in detail.

\begin{verbatim}
> java edu.byu.ece.edif.jedif.JEdifBuild --help
Options:
  [-h|--help]
  [-v|--version]

  <input_file>
  [(-o|--output) <output_file>]
  
  [(-d|--dir) dir1,dir2,...,dirN ]
  [(-f|--file) file1,file2,...,fileN ]

  [--no_flatten]
  [--no_open_pins]
  [--blackboxes]
  [--no_delete_cells]
  [--pack_registers <{i|o|b|n}>]

  [--replace_luts]
  [--remove_fmaps]
  [--remove_rlocs]
  [--remove_hl]
  [--hl_constant <{0|1}>]
  [--hl_use_port <hl_port_name>]
  [--hl_no_tag_constant]

  [(-p|--part) <part>]

  [--write_config <config_file>]
  [--use_config <config_file>]

  [--log <logfile>]
  [--debug[:<debug_log>]]
  [(-V|--verbose) <{1|2|3|4|5}>]
  [--append_log]
\end{verbatim}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{File options: input, output, etc.}
The following options specify the top-level input EDIF file, any auxiliary EDIF
files, and the destination EDIF file.

\subsubsection{\texttt{<input\_file>}}
Filename and path to the EDIF source file containing the top-level cell to be 
converted. This is the only required parameter.

Allowed filename extensions are:
\begin{itemize}
  \item Parsable EDIF: edn,edf,ndf
  \item Binary netlist (Blackboxes): ngc,ngo
  \item Blackbox Utilization: bb
\end{itemize}

Parsable EDIF files will be parsed and included in the algorithms.
Binary netlist files are not parsable by JEdifBuild, but the program
recognizes them as blackboxes, and will not complain about not finding
the entity.  Blackbox utilization files allow the user to specify the
resource use of the blackboxes to help in the utilization estimate and
partial tmr algorithms.  The file format is ``Resource:Number''.
Below is an example:

myblackbox.bb:\\
\begin{verbatim}
  BRAM:1
  FF:400
  LUT:100
\end{verbatim}

This entity, named myblackbox, uses 1 BRAM, 400 Flipflops and 100 LUTS

\subsubsection{\texttt{(-o|--output) <output\_file>}}
Filename and path to the jedif output file.

Default: \texttt{<input file>.jedif} in the current working directory.

\subsubsection{\texttt{(-d|--dir) dir1,dir2,\ldots,dir3}}
Comma-separated list of directories containing external EDIF files
referenced by the top-level EDIF file. The current working directory
is included by default and need not be specified. Multiple \texttt{-d}
options may be specified.

Example: \texttt{-d aux\_files,/usr/share/edif/common -d
  moreEdifFiles/}

\subsubsection{\texttt{(-f|--file) file1,file2,\ldots,fileN}}
Similar to the previous option, but rather than specifying directories to 
search, each external EDIF file is named explicitly---including the path to the 
file. Multiple \texttt{-f} options may be specified.

Example: \texttt{-f multBox.edn,src/adder.edf -f /usr/share/edif/blackBox.edf}.

\subsection{Maintenance Options}
The following options allow some control over what happens during the 
conversion process
  
\subsubsection{\texttt{--no\_flatten}}
By default, JEdifBuild will flatten the EDIF files. Flattening is required by the 
TMR tools, but other applications may wish to keep the hierarchical
design. 

\subsubsection{\texttt{--no\_open\_pins}}
Do not allow the parser to infer open pins on black box definitions.

\subsubsection{\texttt{--blackboxes}}
Allow parser to continue if blackbox definitions are not found.

\subsubsection{\texttt{--no\_delete\_cells}}
By default JEdifBuild will remove unused cells to reduce the size of
the final .jedif file. However, the user can request that these cells
be retained for future use.

\subsubsection{\texttt{--pack\_registers} \{i\textbar o\textbar b\textbar n\}}
By default, the BL-TMR tool treats all ports on the input EdifCell as top-level
ports (those that will be the inputs and outputs of the FPGA). The half-latch 
tool must therefore treat any FFs that will be packed into the IOBs differently
than other FFs (at least with Virtex devices). This option allows the user to
specify which IOBs the registers should be packed into: inputs (\emph{i}),
outputs (\emph{o}), both (\emph{b}), or none (\emph{n}). The default is to pack
both input and output registers.

\subsection{Sterilize Options}

\subsubsection{\texttt{--replace\_luts}}
When this option is specified, the tool replaces LUT RAMs and SRLs
with flip-flop equivalents. This option is useful because bitstream
scrubbing cannot be used with designs that contain LUT RAMs or SRLs.

\subsubsection{\texttt{--remove\_fmaps}}
Remove FMAPs from the input design.

\subsubsection{\texttt{--remove\_rlocs}}
Remove ALL RLOCs in the design.  The replication tools will not work
correctly if a design contains RLOCs.

\subsubsection{\texttt{--remove\_hl}}
Remove half-latches in the input design before performing replication.

Note: Not \emph{all} half-latches can be removed at the EDIF 
level for all architectures. Some post-processing may be necessary.

\subsubsection{\texttt{--hl\_const} $\{0,1\}$}
Sets the polarity of the half-latch constant to be used, whether an 
internally-generated constant or a top-level port. 

Valid options are \texttt{0} and \texttt{1}. Default: \texttt{0}.

\subsubsection{\texttt{--hl\_use\_port <hl\_port\_name>}}
Specify a top-level port to use in place of half-latches when 
using half-latch removal. The top-level port will have the name specified with 
this option and the polarity (1 or 0) specified with the \texttt{--hl\_const} 
option.

\subsubsection{\texttt{--hl\_no\_tag\_constant}}
When half-latch removal is used, a constant comes from either a
constant generator cell (ROM$16$X$1$) or a port specified by the
user. In either case, the input buffer for the port or the generator
cell should be triplicated (or duplicated) to ensure reliability. By
default, such instances are tagged with an EDIF property called
`\texttt{half\_latch\_constant}' so that they can be automatically
selected for replication by JEdifNMRSelection later in case partial
replication is used. This option disables the default behavior of
tagging safe constant instances with this property.

\input{option_Technology}
\input{option_ConfigFile}
\input{option_Logfile}

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% LocalWords:  BYU LANL BL-TMR EDIF FPGA TMR OBUF IBUF BUFG IBUFG LUTs
% LocalWords:  SCC SCCs FFs UCF Xilinx java JHDL netlister IOB IBUFs
% LocalWords:  OBUFs logfile INOUT TMR'd tmr txt JEdifBuild jedif edn edf dir


